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MM74C73 * MM74C76 Dual J-K Flip-Flops with Clear and Preset
October 1987 Revised January 1999
MM74C73 * MM74C76 Dual J-K Flip-Flops with Clear and Preset
General Description
The MM74C73 and MM74C76 dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement transistors. Each flip-flop has independent J, K, clock and clear inputs and Q and Q outputs. The MM74C76 flip flops also include preset inputs and are supplied in 16 pin packages. This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input.
Features
s Supply voltage range: s High noise immunity: 3V to 15V Drive 2 LPTTL loads 0.45 VCC (typ.) s Tenth power TTL compatible: s Low power: 50 nW (typ.) s Medium speed operation: 10 MHz (typ.)
Applications
* Automotive * Data terminals * Instrumentation * Medical electronics * Alarm systems * Industrial electronics * Remote metering * Computers
Ordering Code:
Order Number MM74C73N MM74C76M MM74C76N Package Number N14A M16A N16E Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
MM74C73 MM74C76
Note: A logic "0" on clear sets Q to a logic "0". Note: A logic "0" on preset sets Q to a logic "1". Note: A logic "0" on clear sets Q to logic "0".
Top View
Top View (c) 1999 Fairchild Semiconductor Corporation DS005884.prf www.fairchildsemi.com
MM74C73 * MM74C76
Truth Tables
tn J 0 0 1 1
tn = bit time before clock pulse tn+1 = bit time after clock pulse
tn+1 K 0 1 0 1 Q Qn 0 1 Qn
Preset 0 0 1 1
Clear 0 1 0 1
Qn 0 1 0 Qn (Note 1)
Qn 0 0 1 Qn (Note 1)
Note 1: No change in output from previous state
Logic Diagrams
MM74C73
MM74C76
Transmission Gate
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MM74C73 * MM74C76
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin Operating Temperature Range Storage Temperature Power Dissipation Dual-In-Line Small Outline Lead Temperature (Soldering, 10 seconds) Operating VCC Range VCC (Max) 260C +3V to 15V 18V 700 mW 500 mW
Note 2: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation.
-0.3V to VCC + 0.3V -40C to +85C -65C to +150C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current Output Source Current Output Sink Current Output Sink Current VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 15V VCC = 15V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = 360 A VCC = 5V, VIN(0) = 0V TA = 25C, VOUT = 0V VCC = 10V, VIN(0) = 0V TA = 25C, VOUT = 0V VCC = 5V, VIN(1) = 5V TA = 25C, VOUT = VCC VCC = 10V, VIN(1) = 10V TA = 25C, VOUT = VCC 8 mA 1.75 mA -8 mA -1.75 2.4 0.4 VCC - 1.5 0.8 -1 0.050 60 4.5 9 0.5 1 1 3.5 8 1.5 2 V V V V V V V V A A A V V V V mA Parameter Conditions Min Typ Max Units
LOW POWER TTL TO CMOS INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
3
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MM74C73 * MM74C76
AC Electrical Characteristics (Note 3)
TA = 25C, CL = 50 pF, unless otherwise noted Symbol CIN tpd0, tpd1 Parameter Input Capacitance Propagation Delay Time to a Logical "0" or Logical "1" from Clock to Q or Q tpd0 tpd tS tH tPW tPW tMAX tr, tf Propagation Delay Time to a Logical "0" from Preset or Clear Propagation Delay Time to a Logical "1" from Preset or Clear Time Prior to Clock Pulse that Data must be Present Time after Clock Pulse that J and K must be Held Minimum Clock Pulse Width tWL = tWH Minimum Preset and Clear Pulse Width Maximum Toggle Frequency Clock Pulse Rise and Fall Time VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V
Note 3: AC Parameters are guaranteed by DC correlated testing.
Conditions Any Input VCC = 5V VCC = 10V
Min
Typ 5 180 70
Max
Units pF
300 110
ns ns
200 80 200 80 110 45 -40 -20 120 50 90 40 2.5 7 4 11
300 130 300 130 175 70 0 0 190 80 130 60
ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
15 5
s s
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MM74C73 * MM74C76
AC Test Circuit
Switching Time Waveforms
CMOS to CMOS
tr = tf = 20 ns
Typical Applications
Ripple Binary Counters
Shift Registers
74C Compatibility
Guaranteed Noise Margin as a Function of VCC
5
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MM74C73 * MM74C76
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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MM74C73 * MM74C76 Dual J-K Flip-Flops with Clear and Preset
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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